mirror of https://git.tukaani.org/xz.git
liblzma: x86 CLMUL CRC: Rewrite
It's faster with both tiny and large buffers and doesn't require disabling any sanitizers. With large buffers the extra speed is from folding four 16-byte chunks in parallel. The 32-bit x86 with MSVC reportedly still needs a workaround. Now the simpler "__asm mov ebx, ebx" trick is enough but it needs to be in lzma_crc64() instead of crc64_arch_optimized(). Thanks to Iouri Kharon for testing and the fix. Thanks to Ilya Kurdyukov for testing the speed with aligned and unaligned buffers on a few x86 processors and on E2K v6. Thanks to Sam James for general feedback. Fixes: https://github.com/tukaani-project/xz/issues/112 Fixes: https://github.com/tukaani-project/xz/issues/122
This commit is contained in:
Lasse Collin
parent
c0e7eaae8d
commit
54eaea5ea4
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@ -133,6 +133,14 @@ crc64_dispatch(const uint8_t *buf, size_t size, uint64_t crc)
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extern LZMA_API(uint64_t)
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lzma_crc64(const uint8_t *buf, size_t size, uint64_t crc)
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{
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#if defined(_MSC_VER) && !defined(__INTEL_COMPILER) && !defined(__clang__) \
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&& defined(_M_IX86) && defined(CRC64_ARCH_OPTIMIZED)
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// VS2015-2022 might corrupt the ebx register on 32-bit x86 when
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// the CLMUL code is enabled. This hack forces MSVC to store and
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// restore ebx. This is only needed here, not in lzma_crc32().
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__asm mov ebx, ebx
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#endif
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#if defined(CRC64_GENERIC) && defined(CRC64_ARCH_OPTIMIZED)
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return crc64_func(buf, size, crc);
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@ -8,10 +8,11 @@
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/// The CRC32 and CRC64 implementations use 32/64-bit x86 SSSE3, SSE4.1, and
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/// CLMUL instructions. This is compatible with Elbrus 2000 (E2K) too.
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///
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/// They were derived from
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/// See the Intel white paper "Fast CRC Computation for Generic Polynomials
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/// Using PCLMULQDQ Instruction" from 2009. The original file seems to be
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/// gone from Intel's website but a version is available here:
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/// https://www.researchgate.net/publication/263424619_Fast_CRC_computation
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/// and the public domain code from https://github.com/rawrunprotected/crc
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/// (URLs were checked on 2023-10-14).
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/// (The link was checked on 2024-06-11.)
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///
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/// While this file has both CRC32 and CRC64 implementations, only one
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/// can be built at a time. The version to build is selected by defining
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@ -21,11 +22,11 @@
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/// unless configured with --disable-assembler. Even then the lookup table
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/// isn't omitted in crc64_table.c since it doesn't know that assembly
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/// code has been disabled.
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///
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/// NOTE: The x86 CLMUL CRC implementation was rewritten for XZ Utils 5.8.0.
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//
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// Authors: Ilya Kurdyukov
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// Hans Jansen
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// Lasse Collin
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// Jia Tan
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// Authors: Lasse Collin
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// Ilya Kurdyukov
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//
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///////////////////////////////////////////////////////////////////////////////
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@ -61,257 +62,277 @@
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#endif
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#define MASK_L(in, mask, r) r = _mm_shuffle_epi8(in, mask)
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#define MASK_H(in, mask, r) \
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r = _mm_shuffle_epi8(in, _mm_xor_si128(mask, vsign))
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#define MASK_LH(in, mask, low, high) \
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MASK_L(in, mask, low); \
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MASK_H(in, mask, high)
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// GCC and Clang would produce good code with _mm_set_epi64x
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// but MSVC needs _mm_cvtsi64_si128 on x86-64.
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#if defined(__i386__) || defined(_M_IX86)
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# define my_set_low64(a) _mm_set_epi64x(0, (a))
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#else
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# define my_set_low64(a) _mm_cvtsi64_si128(a)
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#endif
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// Align it so that the whole array is within the same cache line.
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// More than one unaligned load can be done from this during the
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// same CRC function call.
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//
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// The bytes [0] to [31] are used with AND to clear the low bytes. (With ANDN
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// those could be used to clear the high bytes too but it's not needed here.)
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//
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// The bytes [16] to [47] are for left shifts.
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// The bytes [32] to [63] are for right shifts.
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alignas(64)
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static uint8_t vmasks[64] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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};
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// *Unaligned* 128-bit load
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crc_attr_target
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static lzma_always_inline void
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crc_simd_body(const uint8_t *buf, const size_t size, __m128i *v0, __m128i *v1,
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const __m128i vfold16, const __m128i initial_crc)
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static inline __m128i
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my_load128(const uint8_t *p)
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{
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// Create a vector with 8-bit values 0 to 15. This is used to
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// construct control masks for _mm_blendv_epi8 and _mm_shuffle_epi8.
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const __m128i vramp = _mm_setr_epi32(
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0x03020100, 0x07060504, 0x0b0a0908, 0x0f0e0d0c);
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// This is used to inverse the control mask of _mm_shuffle_epi8
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// so that bytes that wouldn't be picked with the original mask
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// will be picked and vice versa.
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const __m128i vsign = _mm_set1_epi8(-0x80);
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// Memory addresses A to D and the distances between them:
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//
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// A B C D
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// [skip_start][size][skip_end]
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// [ size2 ]
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//
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// A and D are 16-byte aligned. B and C are 1-byte aligned.
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// skip_start and skip_end are 0-15 bytes. size is at least 1 byte.
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//
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// A = aligned_buf will initially point to this address.
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// B = The address pointed by the caller-supplied buf.
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// C = buf + size == aligned_buf + size2
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// D = buf + size + skip_end == aligned_buf + size2 + skip_end
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const size_t skip_start = (size_t)((uintptr_t)buf & 15);
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const size_t skip_end = (size_t)((0U - (uintptr_t)(buf + size)) & 15);
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const __m128i *aligned_buf = (const __m128i *)(
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(uintptr_t)buf & ~(uintptr_t)15);
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// If size2 <= 16 then the whole input fits into a single 16-byte
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// vector. If size2 > 16 then at least two 16-byte vectors must
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// be processed. If size2 > 16 && size <= 16 then there is only
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// one 16-byte vector's worth of input but it is unaligned in memory.
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//
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// NOTE: There is no integer overflow here if the arguments
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// are valid. If this overflowed, buf + size would too.
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const size_t size2 = skip_start + size;
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// Masks to be used with _mm_blendv_epi8 and _mm_shuffle_epi8:
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// The first skip_start or skip_end bytes in the vectors will have
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// the high bit (0x80) set. _mm_blendv_epi8 and _mm_shuffle_epi8
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// will produce zeros for these positions. (Bitwise-xor of these
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// masks with vsign will produce the opposite behavior.)
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const __m128i mask_start
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= _mm_sub_epi8(vramp, _mm_set1_epi8((char)skip_start));
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const __m128i mask_end
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= _mm_sub_epi8(vramp, _mm_set1_epi8((char)skip_end));
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// Get the first 1-16 bytes into data0. If loading less than 16
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// bytes, the bytes are loaded to the high bits of the vector and
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// the least significant positions are filled with zeros.
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const __m128i data0 = _mm_blendv_epi8(_mm_load_si128(aligned_buf),
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_mm_setzero_si128(), mask_start);
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aligned_buf++;
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__m128i v2, v3;
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if (size <= 16) {
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// Right-shift initial_crc by 1-16 bytes based on "size"
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// and store the result in v1 (high bytes) and v0 (low bytes).
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//
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// NOTE: The highest 8 bytes of initial_crc are zeros so
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// v1 will be filled with zeros if size >= 8. The highest
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// 8 bytes of v1 will always become zeros.
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//
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// [ v1 ][ v0 ]
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// [ initial_crc ] size == 1
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// [ initial_crc ] size == 2
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// [ initial_crc ] size == 15
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// [ initial_crc ] size == 16 (all in v0)
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const __m128i mask_low = _mm_add_epi8(
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vramp, _mm_set1_epi8((char)(size - 16)));
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MASK_LH(initial_crc, mask_low, *v0, *v1);
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if (size2 <= 16) {
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// There are 1-16 bytes of input and it is all
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// in data0. Copy the input bytes to v3. If there
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// are fewer than 16 bytes, the low bytes in v3
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// will be filled with zeros. That is, the input
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// bytes are stored to the same position as
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// (part of) initial_crc is in v0.
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MASK_L(data0, mask_end, v3);
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} else {
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// There are 2-16 bytes of input but not all bytes
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// are in data0.
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const __m128i data1 = _mm_load_si128(aligned_buf);
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// Collect the 2-16 input bytes from data0 and data1
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// to v2 and v3, and bitwise-xor them with the
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// low bits of initial_crc in v0. Note that the
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// the second xor is below this else-block as it
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// is shared with the other branch.
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MASK_H(data0, mask_end, v2);
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MASK_L(data1, mask_end, v3);
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*v0 = _mm_xor_si128(*v0, v2);
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}
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*v0 = _mm_xor_si128(*v0, v3);
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*v1 = _mm_alignr_epi8(*v1, *v0, 8);
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} else {
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// There is more than 16 bytes of input.
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const __m128i data1 = _mm_load_si128(aligned_buf);
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const __m128i *end = (const __m128i*)(
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(const char *)aligned_buf - 16 + size2);
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aligned_buf++;
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MASK_LH(initial_crc, mask_start, *v0, *v1);
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*v0 = _mm_xor_si128(*v0, data0);
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*v1 = _mm_xor_si128(*v1, data1);
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while (aligned_buf < end) {
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*v1 = _mm_xor_si128(*v1, _mm_clmulepi64_si128(
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*v0, vfold16, 0x00));
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*v0 = _mm_xor_si128(*v1, _mm_clmulepi64_si128(
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*v0, vfold16, 0x11));
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*v1 = _mm_load_si128(aligned_buf++);
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}
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if (aligned_buf != end) {
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MASK_H(*v0, mask_end, v2);
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MASK_L(*v0, mask_end, *v0);
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MASK_L(*v1, mask_end, v3);
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*v1 = _mm_or_si128(v2, v3);
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}
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*v1 = _mm_xor_si128(*v1, _mm_clmulepi64_si128(
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*v0, vfold16, 0x00));
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*v0 = _mm_xor_si128(*v1, _mm_clmulepi64_si128(
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*v0, vfold16, 0x11));
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*v1 = _mm_srli_si128(*v0, 8);
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}
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return _mm_loadu_si128((const __m128i *)p);
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}
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/////////////////////
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// x86 CLMUL CRC32 //
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/////////////////////
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// Keep the highest "count" bytes as is and clear the remaining low bytes.
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crc_attr_target
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static inline __m128i
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keep_high_bytes(__m128i v, size_t count)
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{
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return _mm_and_si128(my_load128((vmasks + count)), v);
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}
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// Shift the 128-bit value left by "amount" bytes (not bits).
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crc_attr_target
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static inline __m128i
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shift_left(__m128i v, size_t amount)
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{
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return _mm_shuffle_epi8(v, my_load128((vmasks + 32 - amount)));
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}
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// Shift the 128-bit value right by "amount" bytes (not bits).
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crc_attr_target
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static inline __m128i
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shift_right(__m128i v, size_t amount)
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{
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return _mm_shuffle_epi8(v, my_load128((vmasks + 32 + amount)));
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}
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crc_attr_target
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static inline __m128i
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fold(__m128i v, __m128i k)
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{
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__m128i a = _mm_clmulepi64_si128(v, k, 0x00);
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__m128i b = _mm_clmulepi64_si128(v, k, 0x11);
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return _mm_xor_si128(a, b);
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}
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crc_attr_target
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static inline __m128i
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fold_xor(__m128i v, __m128i k, const uint8_t *buf)
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{
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return _mm_xor_si128(my_load128(buf), fold(v, k));
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}
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#if BUILDING_CRC_CLMUL == 32
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crc_attr_target
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static uint32_t
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crc32_arch_optimized(const uint8_t *buf, size_t size, uint32_t crc)
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{
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// The code assumes that there is at least one byte of input.
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if (size == 0)
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return crc;
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// See crc_clmul_consts_gen.c.
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const __m128i vfold16 = _mm_set_epi64x(0xccaa009e, 0xae689191);
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const __m128i mu_p = _mm_set_epi64x(
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(int64_t)0xb4e5b025f7011641, 0x1db710640);
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__m128i v0, v1;
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crc_simd_body(buf, size, &v0, &v1, vfold16,
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_mm_cvtsi32_si128((int32_t)~crc));
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v1 = _mm_xor_si128(
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_mm_clmulepi64_si128(v0, vfold16, 0x10), v1); // xxx0
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v0 = _mm_clmulepi64_si128(v1, mu_p, 0x10); // v1 * mu
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v0 = _mm_clmulepi64_si128(v0, mu_p, 0x00); // v0 * p
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v0 = _mm_xor_si128(v0, v1);
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return ~(uint32_t)_mm_extract_epi32(v0, 2);
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}
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#endif // BUILDING_CRC_CLMUL == 32
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/////////////////////
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// x86 CLMUL CRC64 //
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/////////////////////
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#if BUILDING_CRC_CLMUL == 64
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// MSVC (VS2015 - VS2022) produces bad 32-bit x86 code from the CLMUL CRC
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// code when optimizations are enabled (release build). According to the bug
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// report, the ebx register is corrupted and the calculated result is wrong.
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// Trying to workaround the problem with "__asm mov ebx, ebx" didn't help.
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// The following pragma works and performance is still good. x86-64 builds
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// and CRC32 CLMUL aren't affected by this problem. The problem does not
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// happen in crc_simd_body() either (which is shared with CRC32 CLMUL anyway).
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//
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// NOTE: Another pragma after crc64_arch_optimized() restores
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// the optimizations. If the #if condition here is updated,
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// the other one must be updated too.
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#if defined(_MSC_VER) && !defined(__INTEL_COMPILER) && !defined(__clang__) \
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&& defined(_M_IX86)
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# pragma optimize("g", off)
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#endif
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#else
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crc_attr_target
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static uint64_t
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crc64_arch_optimized(const uint8_t *buf, size_t size, uint64_t crc)
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#endif
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{
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// The code assumes that there is at least one byte of input.
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// We will assume that there is at least one byte of input.
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if (size == 0)
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return crc;
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// See crc_clmul_consts_gen.c.
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const __m128i vfold16 = _mm_set_epi64x(
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#if BUILDING_CRC_CLMUL == 32
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const __m128i fold512 = _mm_set_epi64x(0x1d9513d7, 0x8f352d95);
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const __m128i fold128 = _mm_set_epi64x(0xccaa009e, 0xae689191);
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const __m128i mu_p = _mm_set_epi64x(
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(int64_t)0xb4e5b025f7011641, 0x1db710640);
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#else
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const __m128i fold512 = _mm_set_epi64x(
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(int64_t)0x081f6054a7842df4, (int64_t)0x6ae3efbb9dd441f3);
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const __m128i fold128 = _mm_set_epi64x(
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(int64_t)0xdabe95afc7875f40, (int64_t)0xe05dd497ca393ae4);
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const __m128i mu_p = _mm_set_epi64x(
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(int64_t)0x9c3e466c172963d5, (int64_t)0x92d8af2baf0e1e84);
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__m128i v0, v1, v2;
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#if defined(__i386__) || defined(_M_IX86)
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crc_simd_body(buf, size, &v0, &v1, vfold16,
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_mm_set_epi64x(0, (int64_t)~crc));
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#else
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// GCC and Clang would produce good code with _mm_set_epi64x
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// but MSVC needs _mm_cvtsi64_si128 on x86-64.
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crc_simd_body(buf, size, &v0, &v1, vfold16,
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_mm_cvtsi64_si128((int64_t)~crc));
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#endif
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v1 = _mm_xor_si128(_mm_clmulepi64_si128(v0, vfold16, 0x10), v1);
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v0 = _mm_clmulepi64_si128(v1, mu_p, 0x10);
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v2 = _mm_clmulepi64_si128(v0, mu_p, 0x00);
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v0 = _mm_xor_si128(_mm_xor_si128(v1, _mm_slli_si128(v0, 8)), v2);
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__m128i v0, v1, v2, v3;
|
||||
|
||||
crc = ~crc;
|
||||
|
||||
if (size < 8) {
|
||||
uint64_t x = crc;
|
||||
size_t i = 0;
|
||||
|
||||
// Checking the bit instead of comparing the size means
|
||||
// that we don't need to update the size between the steps.
|
||||
if (size & 4) {
|
||||
x ^= read32le(buf);
|
||||
buf += 4;
|
||||
i = 32;
|
||||
}
|
||||
|
||||
if (size & 2) {
|
||||
x ^= (uint64_t)read16le(buf) << i;
|
||||
buf += 2;
|
||||
i += 16;
|
||||
}
|
||||
|
||||
if (size & 1)
|
||||
x ^= (uint64_t)*buf << i;
|
||||
|
||||
v0 = my_set_low64((int64_t)x);
|
||||
v0 = shift_left(v0, 8 - size);
|
||||
|
||||
} else if (size < 16) {
|
||||
v0 = my_set_low64((int64_t)(crc ^ read64le(buf)));
|
||||
|
||||
// NOTE: buf is intentionally left 8 bytes behind so that
|
||||
// we can read the last 1-7 bytes with read64le(buf + size).
|
||||
size -= 8;
|
||||
|
||||
// Handling 8-byte input specially is a speed optimization
|
||||
// as the clmul can be skipped. A branch is also needed to
|
||||
// avoid a too high shift amount.
|
||||
if (size > 0) {
|
||||
const size_t padding = 8 - size;
|
||||
uint64_t high = read64le(buf + size) >> (padding * 8);
|
||||
|
||||
#if defined(__i386__) || defined(_M_IX86)
|
||||
// Simple but likely not the best code for 32-bit x86.
|
||||
v0 = _mm_insert_epi32(v0, (int32_t)high, 2);
|
||||
v0 = _mm_insert_epi32(v0, (int32_t)(high >> 32), 3);
|
||||
#else
|
||||
v0 = _mm_insert_epi64(v0, (int64_t)high, 1);
|
||||
#endif
|
||||
|
||||
v0 = shift_left(v0, padding);
|
||||
|
||||
v1 = _mm_srli_si128(v0, 8);
|
||||
v0 = _mm_clmulepi64_si128(v0, fold128, 0x10);
|
||||
v0 = _mm_xor_si128(v0, v1);
|
||||
}
|
||||
} else {
|
||||
v0 = my_set_low64((int64_t)crc);
|
||||
|
||||
// To align or not to align the buf pointer? If the end of
|
||||
// the buffer isn't aligned, aligning the pointer here would
|
||||
// make us do an extra folding step with the associated byte
|
||||
// shuffling overhead. The cost of that would need to be
|
||||
// lower than the benefit of aligned reads. Testing on an old
|
||||
// Intel Ivy Bridge processor suggested that aligning isn't
|
||||
// worth the cost but it likely depends on the processor and
|
||||
// buffer size. Unaligned loads (MOVDQU) should be fast on
|
||||
// x86 processors that support PCLMULQDQ, so we don't align
|
||||
// the buf pointer here.
|
||||
|
||||
// Read the first (and possibly the only) full 16 bytes.
|
||||
v0 = _mm_xor_si128(v0, my_load128(buf));
|
||||
buf += 16;
|
||||
size -= 16;
|
||||
|
||||
if (size >= 48) {
|
||||
v1 = my_load128(buf);
|
||||
v2 = my_load128(buf + 16);
|
||||
v3 = my_load128(buf + 32);
|
||||
buf += 48;
|
||||
size -= 48;
|
||||
|
||||
while (size >= 64) {
|
||||
v0 = fold_xor(v0, fold512, buf);
|
||||
v1 = fold_xor(v1, fold512, buf + 16);
|
||||
v2 = fold_xor(v2, fold512, buf + 32);
|
||||
v3 = fold_xor(v3, fold512, buf + 48);
|
||||
buf += 64;
|
||||
size -= 64;
|
||||
}
|
||||
|
||||
v0 = _mm_xor_si128(v1, fold(v0, fold128));
|
||||
v0 = _mm_xor_si128(v2, fold(v0, fold128));
|
||||
v0 = _mm_xor_si128(v3, fold(v0, fold128));
|
||||
}
|
||||
|
||||
while (size >= 16) {
|
||||
v0 = fold_xor(v0, fold128, buf);
|
||||
buf += 16;
|
||||
size -= 16;
|
||||
}
|
||||
|
||||
if (size > 0) {
|
||||
// We want the last "size" number of input bytes to
|
||||
// be at the high bits of v1. First do a full 16-byte
|
||||
// load and then mask the low bytes to zeros.
|
||||
v1 = my_load128(buf + size - 16);
|
||||
v1 = keep_high_bytes(v1, size);
|
||||
|
||||
// Shift high bytes from v0 to the low bytes of v1.
|
||||
//
|
||||
// Alternatively we could replace the combination
|
||||
// keep_high_bytes + shift_right + _mm_or_si128 with
|
||||
// _mm_shuffle_epi8 + _mm_blendv_epi8 but that would
|
||||
// require larger tables for the masks. Now there are
|
||||
// three loads (instead of two) from the mask tables
|
||||
// but they all are from the same cache line.
|
||||
v1 = _mm_or_si128(v1, shift_right(v0, size));
|
||||
|
||||
// Shift high bytes of v0 away, padding the
|
||||
// low bytes with zeros.
|
||||
v0 = shift_left(v0, 16 - size);
|
||||
|
||||
v0 = _mm_xor_si128(v1, fold(v0, fold128));
|
||||
}
|
||||
|
||||
v1 = _mm_srli_si128(v0, 8);
|
||||
v0 = _mm_clmulepi64_si128(v0, fold128, 0x10);
|
||||
v0 = _mm_xor_si128(v0, v1);
|
||||
}
|
||||
|
||||
// Barrett reduction
|
||||
|
||||
#if BUILDING_CRC_CLMUL == 32
|
||||
v1 = _mm_clmulepi64_si128(v0, mu_p, 0x10); // v0 * mu
|
||||
v1 = _mm_clmulepi64_si128(v1, mu_p, 0x00); // v1 * p
|
||||
v0 = _mm_xor_si128(v0, v1);
|
||||
return ~(uint32_t)_mm_extract_epi32(v0, 2);
|
||||
#else
|
||||
// Because p is 65 bits but one bit doesn't fit into the 64-bit
|
||||
// half of __m128i, finish the second clmul by shifting v1 left
|
||||
// by 64 bits and xorring it to the final result.
|
||||
v1 = _mm_clmulepi64_si128(v0, mu_p, 0x10); // v0 * mu
|
||||
v2 = _mm_slli_si128(v1, 8);
|
||||
v1 = _mm_clmulepi64_si128(v1, mu_p, 0x00); // v1 * p
|
||||
v0 = _mm_xor_si128(v0, v2);
|
||||
v0 = _mm_xor_si128(v0, v1);
|
||||
#if defined(__i386__) || defined(_M_IX86)
|
||||
return ~(((uint64_t)(uint32_t)_mm_extract_epi32(v0, 3) << 32) |
|
||||
(uint64_t)(uint32_t)_mm_extract_epi32(v0, 2));
|
||||
#else
|
||||
return ~(uint64_t)_mm_extract_epi64(v0, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(_MSC_VER) && !defined(__INTEL_COMPILER) && !defined(__clang__) \
|
||||
&& defined(_M_IX86)
|
||||
# pragma optimize("", on)
|
||||
#endif
|
||||
|
||||
#endif // BUILDING_CRC_CLMUL == 64
|
||||
}
|
||||
|
||||
|
||||
// Inlining this function duplicates the function body in crc32_resolve() and
|
||||
|
|
|
|||
Loading…
Reference in New Issue