mirror of https://git.tukaani.org/xz.git
liblzma: Range decoder: Add x86-64 inline assembly.
It's compatible with GCC and Clang.
This commit is contained in:
Lasse Collin
parent
cba2edc991
commit
3182a330c1
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@ -416,4 +416,495 @@ do { \
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t_offset &= ~t_match_bit ^ rc_mask)
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*/
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////////////
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// x86-64 //
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////////////
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#if defined(__x86_64__) && (defined(__GNUC__) || defined(__clang__))
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// rc_asm_y and rc_asm_n are used as arguments to macros to control which
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// strings to include or omit.
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#define rc_asm_y(str) str
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#define rc_asm_n(str)
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// There are a few possible variations for normalization.
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// This is the smallest variant which is also used by LZMA SDK.
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//
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// - This has partial register write (the MOV from (%[in_ptr])).
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//
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// - INC saves one byte in code size over ADD. False dependency on
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// partial flags from INC shouldn't become a problem on any processor
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// because the instructions after normalization don't read the flags
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// until SUB which sets all flags.
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//
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#define rc_asm_normalize \
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"cmp %[top_value], %[range]\n\t" \
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"jae 1f\n\t" \
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"shl %[shift_bits], %[code]\n\t" \
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"mov (%[in_ptr]), %b[code]\n\t" \
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"shl %[shift_bits], %[range]\n\t" \
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"inc %[in_ptr]\n" \
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"1:\n"
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// rc_asm_calc(prob) is roughly equivalent to the C version of rc_if_0(prob)...
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//
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// rc_bound = (rc.range >> RC_BIT_MODEL_TOTAL_BITS) * (prob);
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// if (rc.code < rc_bound)
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//
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// ...but the bound is stored in "range":
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//
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// t0 = range;
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// range = (range >> RC_BIT_MODEL_TOTAL_BITS) * (prob);
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// t0 -= range;
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// t1 = code;
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// code -= range;
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//
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// The carry flag (CF) from the last subtraction holds the negation of
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// the decoded bit (if CF==0 then the decoded bit is 1).
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// The values in t0 and t1 are needed for rc_update_0(prob) and
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// rc_update_1(prob). If the bit is 0, rc_update_0(prob)...
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//
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// rc.range = rc_bound;
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//
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// ...has already been done but the "code -= range" has to be reverted using
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// the old value stored in t1. (Also, prob needs to be updated.)
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//
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// If the bit is 1, rc_update_1(prob)...
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//
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// rc.range -= rc_bound;
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// rc.code -= rc_bound;
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//
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// ...is already done for "code" but the value for "range" needs to be taken
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// from t0. (Also, prob needs to be updated here as well.)
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//
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// The assignments from t0 and t1 can be done in a branchless manner with CMOV
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// after the instructions from this macro. The CF from SUB tells which moves
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// are needed.
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#define rc_asm_calc(prob) \
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"mov %[range], %[t0]\n\t" \
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"shr %[bit_model_total_bits], %[range]\n\t" \
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"imul %[" prob "], %[range]\n\t" \
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"sub %[range], %[t0]\n\t" \
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"mov %[code], %[t1]\n\t" \
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"sub %[range], %[code]\n\t"
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// Also, prob needs to be updated: The update math depends on the decoded bit.
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// It can be expressed in a few slightly different ways but this is fairly
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// convenient here:
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//
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// prob -= (prob + (bit ? 0 : RC_BIT_MODEL_OFFSET)) >> RC_MOVE_BITS;
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//
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// To do it in branchless way when the negation of the decoded bit is in CF,
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// both "prob" and "prob + RC_BIT_MODEL_OFFSET" are needed. Then the desired
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// value can be picked with CMOV. The addition can be done using LEA without
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// affecting CF.
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//
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// (This prob update method is a tiny bit different from LZMA SDK 23.01.
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// In the LZMA SDK a single register is reserved solely for a constant to
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// be used with CMOV when updating prob. That is fine since there are enough
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// free registers to do so. The method used here uses one fewer register,
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// which is valuable with inline assembly.)
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//
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// * * *
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//
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// In bittree decoding, each (unrolled) loop iteration decodes one bit
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// and needs one prob variable. To make it faster, the prob variable of
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// the iteration N+1 is loaded during iteration N. There are two possible
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// prob variables to choose from for N+1. Both are loaded from memory and
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// the correct one is chosen with CMOV using the same CF as is used for
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// other things described above.
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//
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// This preloading/prefetching requires an extra register. To avoid
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// useless moves from "preloaded prob register" to "current prob register",
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// the macros swap between the two registers for odd and even iterations.
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//
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// * * *
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//
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// Finally, the decoded bit has to be stored in "symbol". Since the negation
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// of the bit is in CF, this can be done with SBB: symbol -= CF - 1. That is,
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// if the decoded bit is 0 (CF==1) the operation is a no-op "symbol -= 0"
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// and when bit is 1 (CF==0) the operation is "symbol -= 0 - 1" which is
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// the same as "symbol += 1".
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//
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// The instructions for all things are intertwined for a few reasons:
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// - freeing temporary registers for new use
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// - not modifying CF too early
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// - instruction scheduling
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//
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// The first and last iterations can cheat a little. For example,
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// on the first iteration "symbol" is known to start from 1 so it
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// doesn't need to be read; it can even be immediately initialized
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// to 2 to prepare for the second iteration of the loop.
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//
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// * * *
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//
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// a = number of the current prob variable (0 or 1)
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// b = number of the next prob variable (1 or 0)
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// *_only = rc_asm_y or _n to include or exclude code marked with them
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#define rc_asm_bittree(a, b, first_only, middle_only, last_only) \
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first_only( \
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"movzw 2(%[probs_base]), %[prob" #a "]\n\t" \
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"mov $2, %[symbol]\n\t" \
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"movzw 4(%[probs_base]), %[prob" #b "]\n\t" \
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) \
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middle_only( \
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/* Note the scaling of 4 instead of 2: */ \
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"movzw (%[probs_base], %q[symbol], 4), %[prob" #b "]\n\t" \
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) \
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last_only( \
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"add %[symbol], %[symbol]\n\t" \
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) \
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\
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rc_asm_normalize \
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rc_asm_calc("prob" #a) \
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\
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"cmovae %[t0], %[range]\n\t" \
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\
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first_only( \
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"movzw 6(%[probs_base]), %[t0]\n\t" \
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"cmovae %[t0], %[prob" #b "]\n\t" \
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) \
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middle_only( \
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"movzw 2(%[probs_base], %q[symbol], 4), %[t0]\n\t" \
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"lea (%q[symbol], %q[symbol]), %[symbol]\n\t" \
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"cmovae %[t0], %[prob" #b "]\n\t" \
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) \
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last_only( \
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/*"lea (%q[symbol], %q[symbol]), %[symbol]\n\t"*/ \
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) \
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\
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"lea %c[bit_model_offset](%q[prob" #a "]), %[t0]\n\t" \
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"cmovb %[t1], %[code]\n\t" \
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"mov %[symbol], %[t1]\n\t" \
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"cmovae %[prob" #a "], %[t0]\n\t" \
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\
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first_only( \
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"sbb $-1, %[symbol]\n\t" \
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) \
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middle_only( \
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"sbb $-1, %[symbol]\n\t" \
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) \
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last_only( \
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"sbb %[last_sbb], %[symbol]\n\t" \
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) \
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\
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"shr %[move_bits], %[t0]\n\t" \
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"sub %[t0], %[prob" #a "]\n\t" \
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/* Scaling of 1 instead of 2 because symbol <<= 1. */ \
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"mov %w[prob" #a "], (%[probs_base], %q[t1], 1)\n\t"
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// NOTE: The order of variables in __asm__ can affect speed and code size.
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#define rc_asm_bittree_n(probs_base_var, final_add, asm_str) \
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do { \
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uint32_t t0; \
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uint32_t t1; \
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uint32_t t_prob0; \
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uint32_t t_prob1; \
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\
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__asm__( \
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asm_str \
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: \
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[range] "+&r"(rc.range), \
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[code] "+&r"(rc.code), \
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[t0] "=&r"(t0), \
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[t1] "=&r"(t1), \
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[prob0] "=&r"(t_prob0), \
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[prob1] "=&r"(t_prob1), \
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[symbol] "=&r"(symbol), \
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[in_ptr] "+&r"(rc_in_ptr) \
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: \
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[probs_base] "r"(probs_base_var), \
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[last_sbb] "n"(-1 - (final_add)), \
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[top_value] "n"(RC_TOP_VALUE), \
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[shift_bits] "n"(RC_SHIFT_BITS), \
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[bit_model_total_bits] "n"(RC_BIT_MODEL_TOTAL_BITS), \
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[bit_model_offset] "n"(RC_BIT_MODEL_OFFSET), \
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[move_bits] "n"(RC_MOVE_BITS) \
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: \
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"cc", "memory"); \
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} while (0)
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#undef rc_bittree3
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#define rc_bittree3(probs_base_var, final_add) \
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rc_asm_bittree_n(probs_base_var, final_add, \
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rc_asm_bittree(0, 1, rc_asm_y, rc_asm_n, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(0, 1, rc_asm_n, rc_asm_n, rc_asm_y) \
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)
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#undef rc_bittree6
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#define rc_bittree6(probs_base_var, final_add) \
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rc_asm_bittree_n(probs_base_var, final_add, \
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rc_asm_bittree(0, 1, rc_asm_y, rc_asm_n, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(0, 1, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(0, 1, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_n, rc_asm_y) \
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)
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#undef rc_bittree8
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#define rc_bittree8(probs_base_var, final_add) \
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rc_asm_bittree_n(probs_base_var, final_add, \
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rc_asm_bittree(0, 1, rc_asm_y, rc_asm_n, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(0, 1, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(0, 1, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(0, 1, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree(1, 0, rc_asm_n, rc_asm_n, rc_asm_y) \
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)
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// Fixed-sized reverse bittree
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//
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// This uses the indexing that constructs the final value in symbol directly.
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// add = 1, 2, 4, 8
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// dcur = -, 4, 8, 16
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// dnext0 = 4, 8, 16, -
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// dnext0 = 6, 12, 24, -
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#define rc_asm_bittree_rev(a, b, add, dcur, dnext0, dnext1, \
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first_only, middle_only, last_only) \
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first_only( \
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"movzw 2(%[probs_base]), %[prob" #a "]\n\t" \
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"xor %[symbol], %[symbol]\n\t" \
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"movzw 4(%[probs_base]), %[prob" #b "]\n\t" \
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) \
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middle_only( \
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"movzw " #dnext0 "(%[probs_base], %q[symbol], 2), " \
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"%[prob" #b "]\n\t" \
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) \
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\
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rc_asm_normalize \
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rc_asm_calc("prob" #a) \
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\
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"cmovae %[t0], %[range]\n\t" \
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\
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first_only( \
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"movzw 6(%[probs_base]), %[t0]\n\t" \
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"cmovae %[t0], %[prob" #b "]\n\t" \
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) \
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middle_only( \
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"movzw " #dnext1 "(%[probs_base], %q[symbol], 2), %[t0]\n\t" \
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"cmovae %[t0], %[prob" #b "]\n\t" \
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) \
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\
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"lea " #add "(%q[symbol]), %[t0]\n\t" \
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"cmovb %[t1], %[code]\n\t" \
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middle_only( \
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"mov %[symbol], %[t1]\n\t" \
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) \
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last_only( \
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"mov %[symbol], %[t1]\n\t" \
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) \
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"cmovae %[t0], %[symbol]\n\t" \
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"lea %c[bit_model_offset](%q[prob" #a "]), %[t0]\n\t" \
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"cmovae %[prob" #a "], %[t0]\n\t" \
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\
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"shr %[move_bits], %[t0]\n\t" \
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"sub %[t0], %[prob" #a "]\n\t" \
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first_only( \
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"mov %w[prob" #a "], 2(%[probs_base])\n\t" \
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) \
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middle_only( \
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"mov %w[prob" #a "], " \
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#dcur "(%[probs_base], %q[t1], 2)\n\t" \
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) \
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last_only( \
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"mov %w[prob" #a "], " \
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#dcur "(%[probs_base], %q[t1], 2)\n\t" \
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)
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#undef rc_bittree_rev4
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#define rc_bittree_rev4(probs_base_var) \
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rc_asm_bittree_n(probs_base_var, 4, \
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rc_asm_bittree_rev(0, 1, 1, -, 4, 6, rc_asm_y, rc_asm_n, rc_asm_n) \
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rc_asm_bittree_rev(1, 0, 2, 4, 8, 12, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree_rev(0, 1, 4, 8, 16, 24, rc_asm_n, rc_asm_y, rc_asm_n) \
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rc_asm_bittree_rev(1, 0, 8, 16, -, -, rc_asm_n, rc_asm_n, rc_asm_y) \
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)
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#undef rc_bit_add_if_1
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#define rc_bit_add_if_1(probs_base_var, dest_var, value_to_add_if_1) \
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do { \
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uint32_t t0; \
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uint32_t t1; \
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uint32_t t2 = (value_to_add_if_1); \
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uint32_t t_prob; \
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uint32_t t_index; \
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\
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__asm__( \
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"movzw (%[probs_base], %q[symbol], 2), %[prob]\n\t" \
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"mov %[symbol], %[index]\n\t" \
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\
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"add %[dest], %[t2]\n\t" \
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"add %[symbol], %[symbol]\n\t" \
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\
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rc_asm_normalize \
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rc_asm_calc("prob") \
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\
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"cmovae %[t0], %[range]\n\t" \
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"lea %c[bit_model_offset](%q[prob]), %[t0]\n\t" \
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"cmovb %[t1], %[code]\n\t" \
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"cmovae %[prob], %[t0]\n\t" \
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\
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"cmovae %[t2], %[dest]\n\t" \
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"sbb $-1, %[symbol]\n\t" \
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\
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"sar %[move_bits], %[t0]\n\t" \
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"sub %[t0], %[prob]\n\t" \
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"mov %w[prob], (%[probs_base], %q[index], 2)" \
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: \
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[range] "+&r"(rc.range), \
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[code] "+&r"(rc.code), \
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[t0] "=&r"(t0), \
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[t1] "=&r"(t1), \
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[prob] "=&r"(t_prob), \
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[index] "=&r"(t_index), \
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[symbol] "+&r"(symbol), \
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[t2] "+&r"(t2), \
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[dest] "+&r"(dest_var), \
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[in_ptr] "+&r"(rc_in_ptr) \
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: \
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[probs_base] "r"(probs_base_var), \
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[top_value] "n"(RC_TOP_VALUE), \
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[shift_bits] "n"(RC_SHIFT_BITS), \
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[bit_model_total_bits] "n"(RC_BIT_MODEL_TOTAL_BITS), \
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[bit_model_offset] "n"(RC_BIT_MODEL_OFFSET), \
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[move_bits] "n"(RC_MOVE_BITS) \
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: \
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"cc", "memory"); \
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} while (0)
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// Literal decoding uses a normal 8-bit bittree but literal with match byte
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// is more complex in picking the probability variable from the correct
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// subtree. This doesn't use preloading/prefetching of the next prob because
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// there are four choices instead of two.
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//
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// FIXME? The first iteration starts with symbol = 1 so it could be optimized
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// by a tiny amount.
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#define rc_asm_matched_literal(nonlast_only) \
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"add %[offset], %[symbol]\n\t" \
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"and %[offset], %[match_bit]\n\t" \
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"add %[match_bit], %[symbol]\n\t" \
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\
|
||||
"movzw (%[probs_base], %q[symbol], 2), %[prob]\n\t" \
|
||||
\
|
||||
"add %[symbol], %[symbol]\n\t" \
|
||||
\
|
||||
nonlast_only( \
|
||||
"xor %[match_bit], %[offset]\n\t" \
|
||||
"add %[match_byte], %[match_byte]\n\t" \
|
||||
) \
|
||||
\
|
||||
rc_asm_normalize \
|
||||
rc_asm_calc("prob") \
|
||||
\
|
||||
"cmovae %[t0], %[range]\n\t" \
|
||||
"lea %c[bit_model_offset](%q[prob]), %[t0]\n\t" \
|
||||
"cmovb %[t1], %[code]\n\t" \
|
||||
"mov %[symbol], %[t1]\n\t" \
|
||||
"cmovae %[prob], %[t0]\n\t" \
|
||||
\
|
||||
nonlast_only( \
|
||||
"cmovae %[match_bit], %[offset]\n\t" \
|
||||
"mov %[match_byte], %[match_bit]\n\t" \
|
||||
) \
|
||||
\
|
||||
"sbb $-1, %[symbol]\n\t" \
|
||||
\
|
||||
"shr %[move_bits], %[t0]\n\t" \
|
||||
/* Undo symbol += match_bit + offset: */ \
|
||||
"and $0x1FF, %[symbol]\n\t" \
|
||||
"sub %[t0], %[prob]\n\t" \
|
||||
\
|
||||
/* Scaling of 1 instead of 2 because symbol <<= 1. */ \
|
||||
"mov %w[prob], (%[probs_base], %q[t1], 1)\n\t"
|
||||
|
||||
|
||||
#undef rc_matched_literal
|
||||
#define rc_matched_literal(probs_base_var, match_byte_value) \
|
||||
do { \
|
||||
uint32_t t0; \
|
||||
uint32_t t1; \
|
||||
uint32_t t_prob; \
|
||||
uint32_t t_match_byte = (match_byte_value) << 1; \
|
||||
uint32_t t_match_bit = t_match_byte; \
|
||||
uint32_t t_offset = 0x100; \
|
||||
symbol = 1; \
|
||||
\
|
||||
__asm__( \
|
||||
rc_asm_matched_literal(rc_asm_y) \
|
||||
rc_asm_matched_literal(rc_asm_y) \
|
||||
rc_asm_matched_literal(rc_asm_y) \
|
||||
rc_asm_matched_literal(rc_asm_y) \
|
||||
rc_asm_matched_literal(rc_asm_y) \
|
||||
rc_asm_matched_literal(rc_asm_y) \
|
||||
rc_asm_matched_literal(rc_asm_y) \
|
||||
rc_asm_matched_literal(rc_asm_n) \
|
||||
: \
|
||||
[range] "+&r"(rc.range), \
|
||||
[code] "+&r"(rc.code), \
|
||||
[t0] "=&r"(t0), \
|
||||
[t1] "=&r"(t1), \
|
||||
[prob] "=&r"(t_prob), \
|
||||
[match_bit] "+&r"(t_match_bit), \
|
||||
[symbol] "+&r"(symbol), \
|
||||
[match_byte] "+&r"(t_match_byte), \
|
||||
[offset] "+&r"(t_offset), \
|
||||
[in_ptr] "+&r"(rc_in_ptr) \
|
||||
: \
|
||||
[probs_base] "r"(probs_base_var), \
|
||||
[top_value] "n"(RC_TOP_VALUE), \
|
||||
[shift_bits] "n"(RC_SHIFT_BITS), \
|
||||
[bit_model_total_bits] "n"(RC_BIT_MODEL_TOTAL_BITS), \
|
||||
[bit_model_offset] "n"(RC_BIT_MODEL_OFFSET), \
|
||||
[move_bits] "n"(RC_MOVE_BITS) \
|
||||
: \
|
||||
"cc", "memory"); \
|
||||
} while (0)
|
||||
|
||||
|
||||
// Doing the loop in asm instead of C seems to help a little.
|
||||
#undef rc_direct
|
||||
#define rc_direct(dest_var, count_var) \
|
||||
do { \
|
||||
uint32_t t0; \
|
||||
uint32_t t1; \
|
||||
\
|
||||
__asm__( \
|
||||
"2:\n\t" \
|
||||
"add %[dest], %[dest]\n\t" \
|
||||
"lea 1(%q[dest]), %[t1]\n\t" \
|
||||
\
|
||||
rc_asm_normalize \
|
||||
\
|
||||
"shr $1, %[range]\n\t" \
|
||||
"mov %[code], %[t0]\n\t" \
|
||||
"sub %[range], %[code]\n\t" \
|
||||
"cmovns %[t1], %[dest]\n\t" \
|
||||
"cmovs %[t0], %[code]\n\t" \
|
||||
"dec %[count]\n\t" \
|
||||
"jnz 2b\n\t" \
|
||||
: \
|
||||
[range] "+&r"(rc.range), \
|
||||
[code] "+&r"(rc.code), \
|
||||
[t0] "=&r"(t0), \
|
||||
[t1] "=&r"(t1), \
|
||||
[dest] "+&r"(dest_var), \
|
||||
[count] "+&r"(count_var), \
|
||||
[in_ptr] "+&r"(rc_in_ptr) \
|
||||
: \
|
||||
[top_value] "n"(RC_TOP_VALUE), \
|
||||
[shift_bits] "n"(RC_SHIFT_BITS) \
|
||||
: \
|
||||
"cc", "memory"); \
|
||||
} while (0)
|
||||
|
||||
#endif // x86_64
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue